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# TSMC CoWoS Capacity Doubles by 2028, but the AI Packaging Crunch Lingers
- URL: https://bytevyte.com/tsmc-cowos-capacity-doubles-by-2028-but-the-ai-packaging-crunch-lingers/
- Published: 2026-09-16T18:07:12.000Z
- Updated: 2026-09-16T18:07:12.000Z
- Description: TSMC CoWoS capacity is set to double to 260,000 wafers a month by late 2028, but packaging stays the AI accelerator bottleneck into 2029.
- Author: Bytevyte Editorial
- Tags: ai-beats

**TSMC CoWoS capacity** is scheduled to double from about 130,000 wafers per month at the end of 2026 to roughly 260,000 by the end of 2028, the single largest lever on how quickly Nvidia, AMD and hyperscaler custom accelerators can reach the market. The foundry is paying for that expansion from a capital budget it has raised to between $60 billion and $64 billion, and it is lifting leading-edge wafer output in parallel: 2nm capacity is projected to grow 22% between late 2026 and mid-2027, 3nm capacity more than 16%, and 3nm wafer volume roughly 70% across an 18-month window.

Packaging deserves more scrutiny than the node numbers. Wafer starts stopped being the binding limit on AI hardware some time ago, and the step that fuses compute dies with HBM stacks onto a single substrate became the choke point instead. TSMC has roughly doubled CoWoS capacity every year since 2023, and demand has still run ahead of supply.

## What TSMC Is Actually Building

The expansion spans more than one site. TrendForce ties the CoWoS build-out to the AP7 packaging plant in Taiwan and to TSMC's Arizona campus, where the company plans to package chips on US soil for US customers. Arizona's advanced packaging line is not expected to reach volume production before 2028, so packaged accelerators sold in America stay dependent on Taiwanese output for at least another two years.

Overseas expansion extends to Japan as well, and the pattern matters more for packaging than for wafers. A fab in Arizona that ships unpackaged dies still routes them through Taiwanese packaging, so localising the front end without localising CoWoS changes little for US buyers. The Arizona packaging line is the piece that alters that arithmetic, and it arrives last.

Older capacity is being converted instead of retired. TSMC is repurposing 200mm fabs for advanced packaging work, and it is building 25 facilities at roughly five times its historical pace. Order visibility for advanced processes reaches into 2029 and 2030, which means the largest customers are committing capital years before the lines exist.

The technical roadmap scales alongside the capacity plan. TSMC produces 5.5-reticle CoWoS packages today. Its April technology symposium materials describe a 14-reticle version for 2028 that would fit roughly 10 large compute dies and 20 HBM stacks into one package, followed by a package larger than 14 reticles in 2029.

| Metric                  | Baseline              | Target                 |
| ----------------------- | --------------------- | ---------------------- |
| CoWoS wafers per month  | \~130,000 (late 2026) | \~260,000 by late 2028 |
| 2nm capacity            | Late 2026             | +22% by mid-2027       |
| 3nm capacity            | Late 2026             | +16% by mid-2027       |
| 3nm wafer output        | Current level         | +70% over 18 months    |
| Annual capital spending | Previous guidance     | $60bn to $64bn         |
| Largest CoWoS package   | 5.5 reticle           | 14 reticle in 2028     |

The two roadmaps pull against each other. Adding 70% more 3nm wafer output increases the number of logic dies that will need packaging, while CoWoS capacity doubles over a longer period. If average package size also grows, the packaging queue lengthens even as every line runs fuller, which is why the supply gap has survived four consecutive years of capacity doubling.

## Why TSMC CoWoS Capacity Alone Won't Clear the Backlog

TSMC chairman C.C. Wei has acknowledged that CoWoS capacity is tight enough to limit growth at Nvidia and AMD, an admission that the foundry itself is gating the AI accelerator ramp ahead of customer demand or wafer supply. The company holds the overwhelming majority of leading-edge 2.5D packaging capacity, and almost all of it sits in Taiwan. Nvidia has the CoWoS lines booked through 2027, leaving every competing accelerator programme to fight over residual allocation.

Package size is rising at the same time. The roadmap moves from 5.5-reticle packages to a 14-reticle design in 2028, roughly two and a half times the substrate area per part. Doubling monthly wafer capacity while the largest packages consume more of each wafer means the count of shippable accelerators rises more slowly than the raw capacity figure implies.

Concentration adds a second constraint. With leading-edge 2.5D packaging clustered in Taiwan, one earthquake or cross-strait disruption would stall accelerator shipments worldwide, and the Arizona line does not close that exposure before 2028\. No alternative supplier can currently qualify at the reticle scale the top accelerators require.

The squeeze also reshapes which products get built. A startup that cannot secure packaging before 2028 faces a choice between shipping a smaller accelerator that fits available capacity and delaying the programme entirely, and both outcomes hand share to incumbents with pre-booked slots. Packaging scarcity filters the AI chip market as effectively as fab allocation does.

## Intel EMIB and the OSAT Alternative

Intel is expanding EMIB packaging capacity and offering it to customers that cannot obtain TSMC CoWoS allocation. The audience is specific: a fabless startup designing an AI ASIC with no CoWoS slot until 2028 can book EMIB capacity instead, provided the design matches Intel's bump pitch, bridge dimensions and thermal envelope.

That compatibility condition is the trade-off. Moving a design from CoWoS to EMIB requires a re-layout of the interposer and a fresh qualification cycle, and for a startup with limited engineering headcount that can consume a full design turn. Intel's capacity is finite too, so EMIB absorbs spillover and does not reset the market.

The qualification burden explains why spillover has not reset pricing. Packaging changes touch the thermal path, the power delivery network and the test flow, so each move away from CoWoS adds engineering cost and schedule risk that offsets the availability gain. For most large accelerator programmes, staying with TSMC and waiting is cheaper than re-engineering for a second source.

ASE, Amkor and SPIL take overflow orders, and Samsung and Chinese firms are building competing 2.5D lines. These suppliers compete on cost and availability, and they relieve pressure in the mid-range of the market where custom inference silicon and networking chips sit. The largest accelerators remain dependent on TSMC.

## What the Timeline Means for Buyers

For hyperscalers, allocation determines accelerator count more than budget does through 2027\. Multi-year commitments signed before lines exist are the only reliable route to volume, and TSMC's order book running into 2029 and 2030 shows that is how the largest buyers are already behaving.

For fabless designers, the decision arrives earlier: design for CoWoS and accept a 2028 slot, or design for EMIB and other packaging options and accept different physical constraints. Waiting for allocation to free up does not shorten the queue, and the queue now extends past most product roadmaps.

For Nvidia and AMD, packaging shapes product mix as much as volume. When large packages consume disproportionate capacity, the incentive tilts toward fewer, larger, higher-margin parts and toward spending scarce CoWoS slots on the accelerators with the best revenue per wafer.

Cost follows scarcity. CoWoS slots allocated to the highest-margin accelerators leave smaller AI chip programmes and second-tier cloud providers at the back of the queue, and a 14-reticle package carrying 20 HBM stacks raises memory content per accelerator well above today's designs.

The milestones to watch are concrete: the AP7 packaging plant ramping in Taiwan, Arizona packaging reaching volume production in 2028, and the first 14-reticle packages shipping that same year. If those three arrive on schedule, the supply gap narrows from 2029\. If any slips, the doubling announced now lands later than the demand curve requires.

## Why this matters

The CoWoS doubling is real capacity, and it will lift AI accelerator supply from 2028 onward. It does not remove the bottleneck before then, and it does not reduce the geographic concentration that leaves the AI hardware chain dependent on a small number of Taiwanese packaging lines. Teams planning AI infrastructure through 2029 should track packaging allocation with the same weight they give GPU demand, because packaging is what gates delivery.

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✔Human Verified

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*Researched and cross-referenced against primary sources by the Bytevyte editorial team. This article was generated with the assistance of artificial intelligence and reviewed by the Bytevyte editorial team.*